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Xilinx ISE 4.1i Delivers Over 300 MHz Performance With Virtex-II FPGAs And Compiles 100,000 Gates per Minute

New Software Provides Industry-First Physical Synthesis and Formal Verification Integration

SAN JOSE, Calif.

Xilinx, Inc. (NASDAQ: XLNX) today announced the availability of its new version 4.1i Integrated Software Environment (ISE). ISE 4.1i proactively solves timing bottlenecks and achieves a quality of results improvement of up to 75 percent over version 3.1i. With Virtex®-II devices, users can now design for clock speeds of greater than 300 MHz. Additionally, Xilinx users now have in their design arsenal next-generation physical synthesis, including Synplicity's Amplify™ and advanced verification capabilities of Synopsys' PrimeTime and Formality. As a result, Xilinx ISE attains the customers' performance needs in record time.

"ISE 4.1i provides unequalled productivity with the industry's fastest runtimes and highest clock frequencies that digital designers demand," said Rich Sevcik, senior vice president and general manager at Xilinx. "For the first time ASIC designers can leverage their investment in the latest ASIC verification and physical synthesis tools for an FPGA solution."

ProActive Timing Closure drives 75 percent performance improvement

ISE now offers a collection of unique technologies, called ProActive Timing Closure, that includes four key technologies: physical synthesis, intelligent place and route algorithms, HDL analysis, and timing cross-probing.

  -- Xilinx worked with strategic partners to enhance physical synthesis for
     programmable logic by using physical placement and timing information
     to optimize all of the design's critical paths. While partnering with
     Xilinx, Synplicty developed its next generation of Amplify software
     with performance improvements up to 40 percent over logic synthesis.
     Designers can expect to achieve an additional 15 percent performance
     improvement with the integration of Synplicity's Total Optimization
     Physical Synthesis, or TOPS TM on Xilinx Virtex-II design performance.
  -- Xilinx own advanced timing driven place and route technology scans the
     design and implements critical paths first, helping to reduce timing
     delays. A new routing algorithm "remembers" which paths were previously
     routed successfully, and then transparently re-routes unsuccessful
     areas to meet overall timing goals.
  -- HDL analysis suggests those modifications to a design's source code and
     constraints to meet the design's timing requirements. Integration with
     Synopsys LEDA tools offers a customizable level of HDL analysis to
     enforce corporate coding standards. Together these enhancements ensure
     good streamlined synthesis results from the source code.
  -- Cross-probing from the Xilinx timing analyzer to either the Xilinx
     Floorplanner or a third party "Technology Viewer," displays the
     critical paths in the design. These paths are highlighted in the
     physical design, the synthesized logic, or the HDL source code itself,
     significantly reducing debug time.

  First with formal verification integration for FPGAs

As design sizes and target devices increase in logic density, verification strategies must advance with them. The ISE 4.1i software includes the first FPGA support for Synopsys Formality and Verplex Conformal LEC (formerly Tuxedo). With formal verification tools for FPGAs at their disposal, customers using ISE 4.1i can rapidly check high-density designs throughout the design flow, greatly speeding up their time-to-market.

Expanded Tool Support

New to ISE's project navigator is the advanced integration with all leading third-party programmable logic synthesis tools. Users can now select from Synopsys FPGA Express, Synplicity's Synplify, or Xilinx own synthesis technology (XST), plus Exemplar's Leonardo Spectrum.

Price, platform and availability

The ISE Series of design tools provide architecture-specific device support for all Xilinx product families including the Spartan®, Virtex, and Virtex-II series, plus the XC9500TM and CoolRunner® CPLD. Designers can target programmable devices up to ten million systems gates, including the largest FPGA available today, the Virtex XC2V6000TM FPGA with six million system gates. ISE software supports Windows98, Windows 2000, and Windows NT; and Chinese, Korean, and Japanese Windows. ISE Foundation and ISE Alliance also support Solaris operating systems. All in-maintenance Xilinx Foundation Series and Alliance Series customers will receive their ISE upgrade with shipments beginning now. New seats of ISE will be available in September with pricing starting at $695. A free, downloadable WebPACK version will be available later this quarter. For more details on how Xilinx simplifies the Programmable Logic design process visit http://www.xilinx.com/ise.

About Xilinx

Xilinx is the leading supplier of complete programmable logic solutions, including advanced integrated circuits, software design tools, predefined system functions delivered as IP cores, and unparalleled field engineering support. Founded in 1984 and headquarters in San Jose, Calif., Xilinx invented field programmable gate arrays (FPGA) and fulfills more than half of the world demand for these devices today. Xilinx solutions enable customers to significantly reduce the time required to develop products for the computer, peripheral, telecommunication, networking, industrial control, instrumentation, high-reliability/military, and consumer markets. For more information, visit the Xilinx web site at http://www.xilinx.com/.



SOURCE: Xilinx, Inc.

Contact: editorial, Ann Duft, +1-408-879-4726, or publicrelations@xilinx.com, or product marketing, Craig Willert, +1-720-652-3439, or craig.willert@xilinx.com, both of Xilinx, Inc.

Web site: http://www.xilinx.com/

Worldwide Media Contacts

Silvia E. Gianelli
Phone: 408-626-4328
Email: silvia.gianelli@xilinx.com


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