SAN JOSE, Calif.
Oct 28, 2004
Xilinx, Inc. (NASDAQ: XLNX) today announced the immediate availability of its next generation PlanAhead™ v2.1 FPGA hierarchical floorplanning and design tool. With full support for the company's Virtex-4 Multi-Platform FPGA family, the new tool dramatically improves maximum clock frequency and time-to-market for leading edge designs through early analysis, feedback and block based incremental flows. The Virtex-4 family -- the industry's fastest FPGA with up to 40% higher logic performance over competing solutions -- can now achieve performance improvements of up to 89% with the use of the PlanAhead tool.
"We broke new ground with the overall methodology that PlanAhead enables for FPGA design, establishing a new standard with respect to productivity and timing closure through our highly automated tool flow. The interactive capabilities of the new tool are a powerful addendum to our toolkit that will greatly enhance designer productivity and maintain our leadership position," said Rich Sevcik, executive vice president of the FPGA Products Group at Xilinx.
The PlanAhead tool provides designers with unique capabilities in analyzing designs early in the design construction phase. Analysis features for timing, utilization, connectivity between modules, clocks, and IO placement significantly reduce design iterations and are intuitively embedded in the comprehensive tool for easy use. These analysis features, combined with the hierarchical floorplanning functionality available in the PlanAhead tool, make a true top-down methodology even more accessible for designers addressing the challenges of complex FPGA design.
PlanAhead has been added to the Xilinx toolkit through the company's Hier Design acquisition. Version 2.1 is the first release of this software since the June 2004 acquisition. The release is strategically timed with the release of Virtex-4 Platform FPGA family. With up to 200,000 logic cells and up to 500 MHz performance, the Virtex-4 family delivers up to 2X the performance and density of any other FPGA family currently in production. The PlanAhead tool has been uniquely positioned by Xilinx to take full advantage of the Virtex-4 feature set. The PlanAhead floorplanning methodology enables designers to first meet timing goals and quickly reproduce correct results on subsequent revision of their designs. Flows for complex devices such as the Virtex-4 family can be greatly enhanced by the block based incremental design capabilities that are seamlessly enabled through the new tool. PlanAhead has added design rule checks (DRC) to catch problems that are found today only through place-and-route runs. DRCs eliminate IO bank rule violations, over-utilized region violations, clock region violations, carry chain violations etc. The early analysis and DRC functionality allow the designer to focus more on the design creation phase and less on the design debug issues.
Pricing & Availability
PlanAhead v2.1 is immediately available and is used with the Integrated Software Environment (ISE) 6.3i FPGA design suite from Xilinx. The tool is priced at $15,000. For more information about the new tool, visit: http://www.xilinx.com/planahead . For more information on the PlanAhead hierarchical floorplanner and to request an evaluation, contact: firstname.lastname@example.org.
About Virtex-4 FPGAs
Enabled by the revolutionary ASMBL (Advanced Silicon Modular Block) architecture, Virtex-4 FPGAs deliver more options than any other FPGA family available today. With more than 100 technical innovations, the Virtex-4 family consists of 17 devices and three domain-optimized platforms: Virtex-4 LX FPGAs for logic-intensive designs, Virtex-4 SX FPGAs for high-performance signal processing, and Virtex-4 FX FPGAs for high-speed serial connectivity and embedded processing. A multi-platform approach makes it possible for customers to select the optimal mix of resources for their application to achieve the highest functionality and performance at the lowest cost.
Xilinx, Inc. is the worldwide leader of programmable logic solutions. Additional Information about Xilinx is available at www.xilinx.com.Photo: NewsCom: http://www.newscom.com/cgi-bin/prnh/20020822/XLNXLOGO
SOURCE: Xilinx, Inc.
CONTACT: Jennifer Van Every of Xilinx, Inc., +1-408-879-7727, or
Web site: http://www.xilinx.com/