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Xilinx XtremeDSP Development Tools Reduce Power and Extend Performance for Virtex-5 DSP Applications

AccelDSP and System Generator for DSP 8.2 Tools support 65nm Virtex-5 LX and LXT FPGAs

Oct 30, 2006

Xilinx, Inc. (NASDAQ: XLNX) today announced the immediate availability of version 8.2 of its XtremeDSP™ development tools. These tools consist of the System Generator for DSP and AccelDSP™, which feature optimized DSP support for XilinxVirtex™-5 LX and LXT, the industry's only 65nm FPGAs. The new version of the software tools enable DSP system designers and algorithm developers, who are unfamiliar with FPGAs, to design, simulate and verify DSP systems, achieving up to 40 percent lower power, 10 percent higher DSP performance and significantly reduced area compared to previous generation Virtex-4 LX FPGAs.

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"We are delivering on our promise to provide world-class DSP design tools and methodologies and this strategic focus is paying enormous dividends for our DSP customers," said Omid Tahernia, vice president and general manager of the Processing Solutions Group at Xilinx. "System Generator and AccelDSP development tools and the Virtex-5 FPGAs are key parts of our solutions strategy. Together they deliver the industry's highest DSP performance, lowest DSP power and area with development times that can be anywhere from five- to thirty-times shorter than traditional RTL design approaches. We're helping our customers gain a significant competitive advantage in their markets."

In addition to supporting the Virtex-5 LX and LXT FPGAs, version 8.2 of AccelDSP and System Generator also include support for the lower cost Spartan- 3E FPGA family from Xilinx. These FPGAs are ideally suited for cost-sensitive applications such as broadband access and home networking that not only require the parallelism of XtremeDSP technology but also the lowest logic cost in order to integrate additional system features such as interfaces, peripherals and control logic.

System Generator for DSP 8.2 Tool

The new 8.2 version of System Generator enables DSP system and algorithm developers -- that do not write VHDL or Verilog -- to develop their designs using MATLAB and Simulink from The MathWorks. Once floating-point modeling is complete, designers quantize it using the Xilinx bit- and cycle-accurate blockset and automatically generate HDL/RTL, netlists or complete bit streams for Xilinx FPGAs, including the new Virtex-5 LX and LXT devices. Finally, designers verify and debug the design on the actual FPGA using high-bandwidth hardware-in-the-loop simulations from within the Simulink environment. New to this release is FIR Compiler 2.0. This parameterized FIR filter complier extends previous versions by adding symmetric coefficient optimization for multi-rate filters reducing DSP48 resources by 50 percent.

AccelDSP 8.2 Tool

AccelDSP is the industry's only tool that enables DSP designers to develop algorithms using MATLAB and synthesize them into RTL. The tool enables automated floating-point to fixed-point generation providing both fixed-point MATLAB and C/C++ simulation models. It also offers algorithmic exploration that lets engineers make tradeoffs between sample rate, performance and area, and provides automatic test bench generation. Once RTL has been generated using the AccelDSP tool, a System Generator library block can be created for integration into a larger system. New to the 8.2 release is the inclusion of the AccelWare™ Algorithmic IP.

In addition, new pricing and packaging for AccelDSP provides a 50 percent cost saving on the tool when purchased separately and more than 60 percent saving when purchased as part of a complete Model-Based Design software package.

About Virtex-5

Virtex-5 LX and LXT FPGAs, the world's first 65nm FPGAs and the latest in the growing Xilinx XtremeDSP device portfolio, are ideal for developing high- performance DSP applications that also need abundant logic resources for integrating additional system and high-speed I/O functions such as motion estimation circuitry for high-definition H.264 encoders. Featuring up to 192 dedicated DSP48E slices (each slice contains an 18x25 multiplier and a 48-bit adder) that operate at speeds up to 550 MHz and consume only 1.38mW of dynamic power for every 100 MHz, Virtex-5 FPGAs are well suited as an ASIC replacement or a DSP co-processor. DSP48E slices form the core of many high performance DSP applications because they can be concatenated to develop highly parallel DSP datapaths. Virtex-5 LXT FPGAs are the industry's first to incorporate low- power serial transceivers, built-in PCI Express® endpoint blocks, and Ethernet media access controller blocks.

Pricing and Availability

Standalone pricing for System Generator starts at $995 and AccelDSP is priced at $4,995. Both System Generator and AccelDSP version 8.2 are available now. Free 30-day evaluations can be found at www.xilinx.com/system_generator and www.xilinx.com/acceldsp, respectively.

Two new XtremeDSP starter bundles are also available to make it easier for DSP system engineers and algorithm developers to gain access to complete front-to-back tool flows as part of the Xilinx Productivity Advantage (XPA) program. XtremeDSP XPA for Model-Based Design includes AccelDSP, System Generator, Integrated Software Environment (ISE™) foundation with ISIM and four days of training all for $9,500. XtremeDSP XPA for MATLAB-Based Design includes AccelDSP, AccelWare Communications and Advanced Math toolkits, ISE foundation with ISIM and two days training for $19,995.

About Xilinx

Xilinx is the worldwide leader in complete programmable logic solutions. For more information, visit www.xilinx.com.

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SOURCE: Xilinx, Inc.

CONTACT: Mark Alden of Xilinx Inc., +1-408-879-7727, or

Web site: http://www.xilinx.com/

Worldwide Media Contacts

Silvia E. Gianelli
Phone: 408-626-4328
Email: silvia.gianelli@xilinx.com


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