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Press Releases

Archives: Search / 2016 / 2015 / 2014 / 2013 / 2012

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May 23, 2016
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Combines 16nm UltraScale+ programmable logic with HBM memory and new accelerator interconnect technology for heterogeneous computing
May 23, 2016
AMD, ARM, Huawei, IBM, Mellanox, Qualcomm, and Xilinx collaborate on new Cache Coherent Interconnect for Accelerators (CCIX) that will allow multiple processor architectures and accelerators to seamlessly share data
May 17, 2016
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Company adds additional board expertise in key industry, technology, and market trends
May 2, 2016
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Applications include 3D object recognition and machine vision enabled by Zynq SoCs and MPSoCs
Apr 19, 2016
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Now available in the Vivado Design Suite 2016.1, SmartConnect technology solves the system interconnect bottlenecks for high performance, multi-million system logic cell designs
Apr 18, 2016
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NGCodec Encoder IP, built with Vivado High Level Synthesis and Kintex UltraScale FPGAs, target the Data Center, Broadcast and Pro A/V markets
Apr 6, 2016
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SuperVessel will include Xilinx SDAccel Development Environment for FPGA acceleration with C, C++, and OpenCL
 

Worldwide Media Contacts

Silvia E. Gianelli
Phone: 408-626-4328
Email: silvia.gianelli@xilinx.com

 

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